The present invention relates to a bit line structure and to a production method therefor, and in particular to a sub-100 nm bit line structure and an associated production method, as can be used in a non-volatile SNOR memory circuit for the respective selective driving of source and drain lines.
In the realization of memory circuits, a distinction is made in principle in terms of the memory architecture, the so-called NAND and NOR architectures being represented most commonly. In both architectures, for example so-called one-transistor memory cells are arranged in matrix-type fashion and driven via so-called word and bit lines.
While in NAND architectures a multiplicity of switching elements or memory elements are connected to one another serially and are driven via a common selection gate or a selection transistor, the respective switching elements in NOR architectures are organized in parallel or in matrix-type fashion, as a result of which each switching element can be selected individually.
FIG. 1A shows a simplified illustration of a so-called SNOR architecture (Selective NOR), in which, in contrast to the NOR architecture with a “common source” construction, the individual switching elements SE1, SE2, . . . are selectively driven via a respective source line SL1, SL2, . . . and via a respective drain line DL1, DL2,. . . . This selective driving is carried out for example by means of respective bit line controllers BLC, which as it were realize the common bit lines BL1, BL2., . . . In this way, it is possible to carry out further shrinks or more extensive integration of semiconductor circuit arrangements, since the SNOR architecture does not rely on a predetermined minimum cell transistor length or channel length.
FIG. 1B shows a simplified illustration of a conventional layout of the SNOR architecture in accordance with FIG. 1A. In accordance with FIG. 1B, the switching elements or memory elements SE1, SE2, . . . are formed in active areas AA of a semiconductor substrate which have a substantially straight strip-type structure. The multiplicity of strip-type active areas AA arranged in columns have superposed on them in rows layer stacks or word line stacks WL1, WL2, . . . that are likewise formed in strip-type fashion. Each crossover point or overlap area between such a strip-type active area AA and a word line stack WL formed in strip-type fashion thus constitutes a multiplicity of semiconductor components or memory elements SE.
Contacts are necessary for making contact with respective drain regions D and source regions S, said contacts usually being formed above the active areas AA, but they may often also reach into an adjoining isolation region STI (Shallow Trench Isolation). In a further overlying layer, which preferably represents a first metallization layer, there are then situated the source lines SL1, SL2, . . . and also the drain lines DL1, DL2, . . . for the respective bit lines BL. In this case, the drain lines are connected to the associated drain regions D of the active area AA via corresponding drain contacts KD, the source lines SL being connected to the associated source regions S via corresponding source contacts KS in the same way.
What is disadvantageous, however, about such a conventional bit line structure is that, on account of the additional source lines, metallization that is more than twice as dense compared with a “common source” architecture is present, which represents a limiting factor for more extensive integration or further shrinks.